数字设计工程师(J10797)

1.Responsible for the digital design of IP modules, IP subsystems, and/or for the chip top level integration 2.RTL design and verification of digital IP modules: Responsible for the implementation of your IP modules, overseeing the module-level verification in close cooperation with the verification team, and debugging failing test cases on module level and SoC top level. 3.Synthesis: deliver a timing clean design with reliable constraints 4.RTL quality checks: provide reports and waivers for LEC, LINT, and CDC checks 5.Contribute to the post-silicon validation of top and IP Subsystems 1.负责IP模块、IP子系统的数字设计，和/或芯片顶层集成。 2.数字IP模块的RTL设计与验证：负责您所承担的IP模块的实现，与验证团队紧密合作，监督模块级验证，并在模块级和SoC顶层对失败的测试案例进行调试。 3.综合：交付一个时序干净且具有可靠约束的设计。 4.RTL质量检查：为LEC、LINT和CDC检查提供报告和豁免。 5.参与芯片及IP子系统的流片后验证。 1.Degree in Electrical Engineering or Computer Science. 2.At least 3 years of experience of hands on RTL design. 3.Working experience in advanced verification methodologies, synthesis, revision control. 4.Must have expert problem solving skills 5.Good team player with ability to work across functional teams, sites, and cultures. 1.拥有电子工程或计算机科学专业学位。 2.具备至少2年RTL设计实战经验。 3.在先进的验证方法学、逻辑综合及版本控制方面拥有工作经验。 4.必须具备专家级的问题解决能力。 5.良好的团队合作精神，能够跨职能团队、跨地域、跨文化开展工作。 职位类别: 社会招聘